The present invention relates to a method and apparatus for verifying the validity of data stored in the volatile portion of the memory of a microcomputer upon restoration of power following a power failure.
Various methods and apparatus have been taught in the art for assuring validity of data stored in volatile memory portions of a microprocessor in view of the increasing number of useable programmable memory features in electrical appliances. In U.S. Pat. No. 4,819,237 it is described that various means such as large capacitors, batteries or other devices are used to provide a five second minimum "data valid time" in order to prevent corruption of volatile memory upon power interruptions of five seconds or less which is said to encompass 87% of all power interruptions. That patent describes a method of compressing all of the data in a verified portion of volatile memory into a bit pattern and then storing the compressed bit pattern in a separately reserved portion of volatile memory to be later verified. Upon resumption of power, a compressed bit pattern for the current data is generated and is then compared to the initial stored bit pattern. If the bit patterns are identical then an additional comparison is made of a fixed bit pattern from non-volatile memory with a fixed bit pattern which was originally copied from non-volatile memory to the reserved portion of volatile memory. If both comparisons show equality, then it is determined that the volatile memory has not become invalid and operation of the microcomputer will resume utilizing the data in the verified portion of the volatile memory.
This device requires a specified reserve space for storage of the compressed bit pattern of the volatile memory as well as the compressed bit pattern obtained from the non-volatile memory. All of the volatile memory outside of the reserved space is compressed and stored in the reserve space for later use.